全球人工智能产业的快速扩张正在引发严重的存储芯片供应紧张，尤其是高带宽内存（HBM）需求激增，使传统DRAM产能面临重新分配的压力。在这一背景下，英特尔前首席执行官帕特·基辛格（Pat Gelsinger）正在押注一种新型内存技术，希望通过改变传统存储单元的设计方式，解决AI芯片长期面临的容量、带宽和功耗问题。
这项技术名为Z2RAM，由美国初创企业Nagare Labs开发。该公司由佐治亚理工学院的研究人员Suman Datta和Shimeng Yu创立，研究基础来自多年来对铁电存储器、电阻式随机存取存储器等新型存储技术的探索。
基辛格目前参与的投资机构Playground Global领投了Nagare Labs的500万美元种子轮融资。他对这项技术表现出相当大的兴趣，认为Z2RAM有机会结合SRAM、DRAM和闪存的优势，打造一种兼具高密度、高速度和可扩展性的新型存储器。
基辛格指出，过去三十年间，广泛商业化应用的主流存储技术并没有出现根本性的变化，SRAM、DRAM和NAND闪存依然构成现代计算设备的存储基础。但随着人工智能计算需求迅速增长，传统存储架构的局限性正在变得越来越明显。
这项技术最重要的突破，在于重新设计了存储单元的电荷保存方式。
传统DRAM通常采用1T1C结构，即一个晶体管搭配一个电容器，通过电容器存储电荷来表示数据。由于电容器中的电荷会随着时间逐渐泄漏，DRAM必须定期刷新数据，而且读取过程具有破坏性，读取之后需要重新写入。
SRAM则采用不同的设计，通常需要六个晶体管组成一个存储单元。它不需要像DRAM那样周期性刷新，读取速度非常快，因此被广泛用于处理器内部的高速缓存。但代价是存储单元面积较大，制造成本高，难以像DRAM和NAND那样实现大规模高密度扩展。
Z2RAM试图在两者之间找到新的平衡。它采用两个晶体管构成存储单元，不再使用传统DRAM中的独立电容器，而是利用第二个晶体管的栅极电容保存电荷。
Nagare Labs联合创始人Suman Datta解释称，这种设计能够实现非破坏性读取。也就是说，读取数据时不需要像传统DRAM那样将存储电荷消耗掉，再执行重新写入操作，因此有望降低访问延迟，并改善整体存储效率。
在密度方面，Nagare Labs预计，第一代Z2RAM的单位面积存储密度可以达到传统SRAM的五倍以上。举例来说，如果相同面积的SRAM能够提供64MB容量，那么采用Z2RAM后，理论上可以将容量提高到320MB左右，同时保持接近SRAM的带宽水平。
这对于人工智能处理器尤其重要。目前，AI加速器越来越依赖HBM提供巨大的内存带宽，但HBM需要复杂的堆叠封装技术，制造成本高，功耗和封装面积也存在限制。
另一方面，部分专门用于AI推理的处理器采用大量片上SRAM，以尽可能减少处理器访问外部内存的延迟。然而，SRAM密度有限，导致芯片必须在有限面积内作出容量与计算单元之间的取舍。
例如，英伟达Groq 3 LPU采用了大量SRAM作为片上存储资源，单颗芯片的SRAM容量约为500MB。按照Nagare Labs的技术设想，如果Z2RAM能够实现预期的五倍密度，那么相同面积便可以容纳数倍于传统SRAM的数据。这可能减少大型AI推理系统对处理器数量的需求，并降低数据在不同芯片之间传输的压力。
Z2RAM的另一个重要特点是采用氧化物半导体材料，并计划通过3D混合键合技术直接集成在计算逻辑芯片上方。
这意味着它不必完全依赖传统内存芯片与处理器分离的架构，而是有机会将高密度存储层直接堆叠在计算芯片附近，缩短数据传输距离。其设计思路与AMD通过3D V-Cache技术在处理器上堆叠额外SRAM缓存有一定相似之处，但Z2RAM希望提供更高的存储密度。
制造工艺方面，Nagare Labs还计划借鉴NAND闪存的垂直堆叠思路，将多个存储层逐层构建起来。与HBM和LPDDR依赖复杂的高密度存储封装不同，公司希望通过氧化物半导体和后端工艺实现相对简单的多层制造。这种方案如果能够成功，将有机会降低大容量片上存储的制造成本。
不过，Z2RAM目前仍处于非常早期的研发阶段。Nagare Labs刚刚完成500万美元种子轮融资，现阶段的成果主要还是实验室原型，尚未进入成熟的芯片制造阶段。
公司正在寻找能够提供研发制造能力的晶圆厂合作伙伴，希望将技术从大学实验室的洁净室环境推进到更大规模的生产验证。按照目前的规划，Nagare Labs希望在未来四年内提供可以工作的Z2RAM存储芯片样品，并争取在未来十年内实现商业化出货。
与此同时，这项技术还面临不少工程挑战。
首先是与计算芯片的集成问题。Z2RAM需要通过3D混合键合与处理器或AI加速器连接，但目前行业尚未形成适用于这种新型存储器的统一接口标准。佐治亚理工学院研究人员表示，如果没有成熟的行业标准，Nagare Labs可能需要自行开发接口技术，这将增加产品设计和商业化的复杂程度。
其次是材料可靠性。氧化物半导体在热稳定性和抗辐射性能方面具有一定优势，但材料内部可能出现原子空位等缺陷。这些微观缺陷可能影响晶体管的阈值电压，即使只有很小的电压变化，也可能导致存储单元出现数据错误。
对于内存产品而言，可靠性往往比实验室中的峰值性能更加重要。任何一种新型存储技术，都必须经过长期的数据保持、读写寿命、温度变化和制造一致性验证，才能真正进入商业市场。
Nagare Labs联合创始人也承认，历史上已经有大量内存初创企业试图挑战传统DRAM和闪存技术，但最终未能成功。即使一项技术在实验室中表现出色，也不意味着它能够通过半导体产业严格的质量标准，并进入现有计算系统的供应链。
基辛格之所以看好Z2RAM，与当前AI产业面临的内存瓶颈密切相关。大型语言模型的训练和推理不仅需要强大的计算能力，还需要持续向处理器输送大量数据。当计算单元的处理速度远远超过内存的数据供应能力时，处理器就必须等待数据，导致昂贵的计算资源无法充分利用。
目前，HBM是解决AI加速器内存带宽问题的主要方案，但它并非没有缺陷。基辛格认为，Z2RAM如果能够实现预期性能，将有机会在存储密度、速度和功耗方面提供不同于现有HBM的解决方案。
值得注意的是，Z2RAM并不是一种能够在短期内解决全球DRAM和HBM供应短缺的技术。即使未来四年能够提供工程样品，距离大规模商业化仍然存在相当长的距离。当前全球内存供应紧张主要来自AI数据中心需求激增，以及三星、SK海力士和美光将更多产能转向HBM和服务器内存产品。
Ars Technica
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如果Z2RAM最终能够实现量产，它更重要的意义可能在于改变未来处理器的存储架构，而不是简单增加传统内存芯片的供应量。它有望让AI处理器在芯片内部获得更大的高速存储空间，减少对外部内存带宽的依赖，并为下一代AI加速器提供新的设计选择。
从SRAM到DRAM，再到NAND闪存，半导体产业已经形成了相对成熟的存储技术体系。Z2RAM试图打破这些技术之间长期存在的性能与密度取舍。不过，目前它仍是一项处于实验室阶段的技术构想，最终能否从科研成果转变为具有竞争力的商业产品，还需要时间和制造工艺的检验。
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The rapid expansion of the global artificial intelligence industry is causing severe strains in the supply of storage chips, particularly the surge in high bandwidth memory (HBM) demand, which puts traditional DRAM capacity under pressure of redistribution. Against this background, Pat Gelsinger, the former CEO of Intel, is in the process of betting on a new memory technology that aims to address the long-standing problems of capacity, bandwidth and power consumption of the AI chip by changing the design of traditional storage units.
The technology, Z2RAM, was developed by Nagare Labs, an American start-up company. The company was founded by Suman Datta and Shimenge Yu, researchers at the Georgia Institute of Technology, and was based on years of exploration of new storage technologies, such as iron and electronic storage, and resistance random access storage.
Playground Global, the investment agency in which Kissinger is currently involved, has invested $5 million in seed ship financing for Nagare Labs. He expressed considerable interest in this technology, considering that Z2RAM had the opportunity to create a new storage device that combined high density, high speed and scalability with the advantages of SRAM, DRAM and flash.
According to Kissinger, there has been no fundamental change in mainstream storage technologies for extensive commercial applications over the past three decades, and SRAM, DRAM and NAND flashbacks continue to form the storage base of modern computing devices. However, with the rapidly growing demand for artificial intelligence computing, the limitations of traditional storage structures are becoming increasingly apparent.
The most important breakthrough in this technology is the redesign of the storage unit ' s charge storage.
Traditional DRAMs usually use a 1T1C structure, i.e. a transistor with a capacitor, which is used to store the charge for data. Since the charge in the capacitors will leak over time, DRAM must regularly update the data and the reading process is destructive, and rewritten after reading.
SRAM uses different designs, usually requiring six transistors to form a storage unit. It does not need to be cyclically refreshed and read very quickly as DRAM, and is therefore widely used for high-speed cache inside the processor. The cost, however, is the size of the storage units and the high cost of manufacturing, making it difficult to achieve large-scale, high-density expansions like DRAM and NAND.
Z2RAM tried to find a new balance between the two. It uses two transistor units to form a storage unit and no longer uses a stand-alone capacitors in the traditional DRAM, but instead uses a second transistor grid to save the charge.
The co-founder of Nagare Labs, Suman Datta, explained that the design could achieve non-destructive reading. In other words, the data need not be read in the same way as traditional DRAMs, before rewriting operations are carried out, so it is expected to reduce access delays and improve overall storage efficiency.
In terms of density, Nagare Labs predicted that the first generation of Z2RAM would have a unit area storage density of more than five times that of traditional SRAM. For example, if SRAM of the same size could provide 64MB capacity, the introduction of Z2RAM would theoretically raise the capacity to about 320MB while maintaining a bandwidth level close to SRAM.
This is particularly important for artificial intelligence processors. Currently, the AI accelerator increasingly relies on HBM to provide large memory bandwidth, but HBM requires complex stacking techniques, high manufacturing costs and limited power consumption and containment area.
On the other hand, some of the processors dedicated to AI reasoning use a large number of SRAMs to minimize delays in processors accessing external memory. However, the limited density of SRAM has resulted in the chip having to make a trade-off between capacity and computing units within a limited area.
For example, Groq 3 LPU uses a large amount of SRAM as a memory resource on a piece, with a single chip of approximately 500 MB. According to Nagare Labs ' technology scenario, if Z2RAM achieves the desired five-fold density, the same area can accommodate several times the traditional SRAM data. This may reduce the demand for processors in large AI reasoning systems and reduce the pressure for data to be transmitted between chips.
Another important feature of Z2RAM is the use of oxide semiconductor materials and plans to integrate directly above the calculated logic chip through 3D hybrid-key technology.
This means that it does not have to rely entirely on the structure of the traditional memory chip that separates it from the processor, but rather has the opportunity to stack the high-density storage layer directly near the computing chip, reducing the distance of data transmission. The idea of design is somewhat similar to the idea of AMD stacking additional SRAMcache on the processor through 3D V-Cache technology, but Z2RAM wishes to provide a higher storage density.
In the manufacturing process, Nagare Labs also plans to build layers of multiple storage layers, drawing on the vertical stacking of NAND flash. Unlike HBM and LPDDR, which rely on complex high-density storage seals, companies wish to achieve relatively simple layers of manufacture through the oxide semiconductor and back-end processes. Such a programme, if successful, would have the opportunity to reduce the manufacturing costs stored on large caps.
However, Z2RAM is still at a very early stage of research and development. Nagare Labs has just completed a $5 million seed ship facility, and the results at this stage are mainly laboratory prototypes and are not yet in the stage of mature chip manufacturing.
The company is looking for a crystal circle partner who can provide research and development manufacturing capacity and hopes to move the technology from a cleaner room environment in a university laboratory to greater production certification. As currently planned, Nagare Labs hopes to provide working Z2RAM samples to store the chips over the next four years and to achieve commercial deliveries within the next 10 years.
At the same time, the technology faces many engineering challenges.
First is the problem of integration with the calculated chip. Z2RAM needs to be connected to the processor or the AI accelerator by a combination of 3D keys, but no uniform interface standards have been developed for this new storage. Researchers at the Institute of Technology in Georgia indicated that, in the absence of mature industry standards, Nagare Labs might need to develop interface technology on its own, which would increase the complexity of product design and commercialization.
The second is material reliability. The oxide semiconductor has some advantages in thermal stability and radiation resistance, but there may be defects in the material, such as atom space. These micro-defects may affect the threshold voltage of transistor tubes, and even small voltage changes may result in data errors in storage units.
For memory products, reliability is often more important than peak performance in laboratories. Any new storage technology requires long-term data maintenance, reading and writing life, temperature change and manufacturing consistency to be truly accessible to the commercial market.
The co-founders of Nagare Labs also acknowledged that there had been a large number of historical memory start-ups that had attempted to challenge traditional DRAM and flash technologies, but that they had failed. Even if a technology is performing well in a laboratory, it does not mean that it can pass through strict quality standards in the semiconductor industry and enter the supply chain of existing computing systems.
Kissinger's appreciation of Z2RAM is closely linked to the existing built-in bottlenecks facing the AI industry. The training and reasoning of large language models require not only a strong computing capability but also the continuous transmission of large amounts of data to processors. When the computing unit is processed at a rate far faster than the memory data supply capacity, the processor has to wait for the data, resulting in the underutilization of expensive computing resources.
At present, HBM is the main solution to the problem of the bandwidth of the AI accelerator, but it is not without defects. According to Kissinger, Z2RAM would have the opportunity to offer solutions different from existing HBMs in terms of storage density, speed and power consumption if it were to achieve the desired performance.
It is noteworthy that Z2RAM is not a technology that can address the global DRAM and HBM supply shortages in the short term. Even if engineering samples were available over the next four years, there would still be a considerable distance from large-scale commercialization. The current strain on global memory supply stems mainly from the surge in demand in the AID data centre and the shift of increased capacity from Samsung, SK Hercules and Mei-ray to HBM and server memory products.
Ars Technica
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If Z2RAM is eventually able to achieve volume production, it may be more important to change the storage structure of future processors rather than simply increasing the supply of traditional memory chips. It is expected to provide greater high-speed storage space for AI processors inside the chip, reduce reliance on external memory bandwidth and provide new design options for the next generation of AI accelerators.
From SRAM to DRAM to the NAND flash, the semiconductor industry has developed a relatively mature storage technology system. Z2RAM seeks to break the long-standing trade-off between performance and density of these technologies. However, it is still a technical concept at the laboratory stage, and it will take time and manufacturing processes to test the eventual transformation from scientific research to competitive commercial products.
Auto-fetched and translated by AI Atlas. All rights belong to the original author.