Weebit Nano 发布 Matrix ReRAM 记忆AI计算研究方案

AI 模型和平台

Weebit Nano 发布 Matrix ReRAM 记忆AI计算研究方案

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Weebit Nano拥有Webit Matrix in-Memory Compute Research Program，使学术和行业研究人员能够访问 reRAM 硬件，以测试不同的方式运行AI计算：在存储数据的地方执行。

该方案提供围绕一个32×32跨栏阵列构建的研究包，支持包括矢量-矩阵乘法，演化，以及溢出神经网络在内的操作。 它针对边缘AI的一个重要硬件问题：通过减少内存和单独处理器之间的重复传输，可以节省多少能量和时间？

这是研究平台发布，而不是完成的商业AI加速器。 Weebit 称技术挑战依然存在，因为内在计算解决方案尚未进入商业市场。 直接的目标是让研究人员从模型和模拟转移到实际的REAM硬件上的实验。

为什么计算内存？

神经网络推论多次将输入与存储的模型权重相结合。 在传统架构中，通过内存层次来移动这些值可以消耗带宽和能量。 内存计算(In-memory computing)，即IMC，寻求在内存数组本身内完成部分工作。

逆向随机存取内存，或ReRAM，使用可编程电阻存储信息。 Weebit的氧化物基电池在电极之间包含一个切换层；应用电压会改变导电路径，从而改变电池的电阻。 存储状态在不连续功率的情况下持续，使得RERAM不易挥发。

在模拟计算研究中，这些电气特性可以做比存储位。 一个阵列可以在它的内存细胞中编码权重，并使用由此产生的电响应参与计算。 它将内存的物理行为与整个神经网络使用的乘积操作联系起来。

目标特别适用于功率和热能预算紧张的装置，包括传感器、工业设备和其他边缘系统。 这并不意味着AI模型的每个部分都在阵列内运行，或者数据运动从完整的系统中消失。

矩阵研究包包含什么

Weebit最初提供两个包：

- Matrix IMC评价套件：一个供希望更接近硬件的研究人员直接访问的评价委员会。

- Matrix IMC快速启动软件包：一个完整的IMC板，一个FPGA子系统，以及样本代码。

两者都包括包装芯片样本、文件以及装有插座的IMC板。 32×32横栏提供了一个可控平台，用于调查编程方法，AI算法，以及神经形态架构，包括尖锐神经网络。

快速启动选项中的FPGA子系统为研究人员提供了可编程的数字硬件与内存阵列并列。 这对于探索基于内存的操作与常规处理而不是试图取代整个计算管道的混合系统是有用的。

与会者将与Weebit分享与ReRAM有关的结果和反馈。 称公司表示，合作的目的是改进技术，为更广泛的研究工作提供信息。 公告未披露套装定价、接受的项目编号或商业加速器交付日期。

将80x电力索赔置于上下文

链接的研究摘要为Weebit的性能声称提供了重要细节。 一家从事耐辐射AI硬件的无名美国公司利用自定义的革命神经网络评价了IMC架构的图像分类工作量。

该比较使用了NVIDIA GeForce RTX 4090 GPU和一个Xilinx ZCU104 FPGA平台。 根据Weebit ReRAM阵列的测量结果，通过应用模型预测了IMC系统一级的结果。

对于这一工作量，分析预测，电力消耗比GPU的执行低约80倍，比FPGA的执行低13倍。 发布的发布单独描述了近百倍的耐性减少。 这些是具体工作量的预测，不是对全商业矩阵加速器在AI任务中优于GPU的独立验证测量。

这种区别是研究方案的核心。 一个有用的数组级结果需要转化为一个完整的系统，在计算控制，数据转换，通信等辅助操作时，保持模型精度。 这些周围的功能也消耗能量和增加耐性。

硬件实验可以揭示什么模拟失败

Weebit CEO Coby Hanoch指出之前与CEA-Leti的合作，包括2019年基于ReRAM的跃进神经网络演示。 矩阵通过向更多的合格研究人员提供定义的硬件平台，扩展了这一研究方向。

神经形态研究者凯文·D·约翰逊(Kevin D. Johnson)，他的工作包括多种和神经形态的计算，称，他希望利用该平台来验证模型与实际硬件对比，并评估系统级别准确性，耐久性和功耗。 他的兴趣包括将ReRAM与其他处理技术相结合。

这种办法反映了实际机会：确定工作量的哪些部分受益于基于内存的计算，然后酌情与其他硬件合并。 研究问题比单项操作是否高效要广泛；它包括由此产生的系统是否提供有用和可重复的应用性能。

Weebit还强调辐射耐受性是调查恶劣环境的ReRAM的一个原因。 某一特定航空航天、防御或医疗部署是否合适仍取决于对完整设计的要求和验证。

示范和研究获取

Weebit计划在2026电子a上演示Matrix IMC，于11月10日至13日在慕尼黑举行。 公司列出Hall C2，第637号站点，其活动页面有演示和会议细节。

这些软件包可供合格的研究人员使用，并将对应用进行评估，以便与方案的研究重点保持一致。 Weebit为未来的参与者提供了一份研究项目申请表。

Matrix的即时贡献是访问硬件，可以测试记忆AI背后的假设。 对于一个围绕降低数据移动成本的领域来说，有价值的证据是，当研究人员进行实际工作量时，测量的准确性、能量使用和耐久性如何维持在一起。

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AI Models & Platforms

Weebit Nano Launches Matrix ReRAM Research Program for In-Memory AI Computing

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Weebit Nano has launched the Weebit Matrix In-Memory Compute Research Program, giving academic and industry researchers access to ReRAM hardware for testing a different way to run AI calculations: perform them where the data is stored.

The program provides research kits built around a 32 × 32 crossbar array, with support for operations including vector-matrix multiplication, convolution, and spiking neural networks. It targets an important hardware question for edge AI: how much energy and time can be saved by reducing repeated transfers between memory and a separate processor?

This is a research-platform launch, rather than a finished commercial AI accelerator. Weebit says technical challenges remain before an in-memory computing solution reaches the commercial market. The immediate objective is to let researchers move from models and simulations to experiments on actual ReRAM hardware.

Why Calculate Inside Memory?

Neural-network inference repeatedly combines inputs with stored model weights. In a conventional architecture, moving those values through the memory hierarchy can consume bandwidth and energy. In-memory computing, or IMC, seeks to perform some of that work within the memory array itself.

Resistive random-access memory, or ReRAM, stores information using programmable electrical resistance. Weebit’s oxide-based cells contain a switching layer between electrodes; applied voltages change the conductive path and therefore the cell’s resistance. The stored state persists without continuous power, making ReRAM non-volatile.

In analog computing research, those electrical properties can do more than store bits. An array can encode weights in its memory cells and use the resulting electrical responses to participate in calculations. That connects the physical behavior of the memory to the multiply-and-accumulate operations used throughout neural networks.

The goal is especially relevant to devices with tight power and thermal budgets, including sensors, industrial equipment, and other edge systems. It does not imply that every part of an AI model runs inside the array or that data movement disappears from the complete system.

What the Matrix Research Kits Include

Weebit is initially offering two packages:

- Matrix IMC Evaluation Package: a direct-access evaluation board for researchers who want closer access to the hardware.

- Matrix IMC Quick-Start Package: a complete IMC board, an FPGA subsystem, and sample code.

Both include packaged chip samples, documentation, and an IMC board with a socket. The 32 × 32 crossbar provides a controlled platform for investigating programming methods, AI algorithms, and neuromorphic architectures, including spiking neural networks.

The FPGA subsystem in the quick-start option gives researchers programmable digital hardware alongside the memory array. That is useful for exploring hybrid systems, where memory-based operations work with conventional processing rather than attempting to replace an entire computing pipeline.

Participants will share ReRAM-related results and feedback with Weebit. The company says that collaboration is intended to improve the technology and inform the wider research effort. The announcement does not disclose kit pricing, accepted-project numbers, or a commercial accelerator delivery date.

Putting the 80× Power Claim in Context

A linked research summary provides important detail behind Weebit’s performance claims. An unnamed U.S. company working on radiation-tolerant AI hardware evaluated an IMC architecture for an image-classification workload using a custom convolutional neural network.

The comparison used an NVIDIA GeForce RTX 4090 GPU and a Xilinx ZCU104 FPGA platform. The IMC system-level results were projected through application modeling based on measurements from a Weebit ReRAM array.

For that workload, the analysis projected approximately 80 times lower power consumption than the GPU implementation and 13 times lower power than the FPGA implementation. The launch release separately describes an almost 100-fold latency reduction. These are workload-specific projections, not independently validated measurements of a complete commercial Matrix accelerator outperforming GPUs across AI tasks.

That distinction is central to the research program. A useful array-level result needs to translate into a complete system that preserves model accuracy while accounting for control, data conversion, communications, and other supporting operations. Those surrounding functions also consume energy and add latency.

Hardware Experiments Can Reveal What Simulations Miss

Weebit CEO Coby Hanoch points to earlier collaboration with CEA-Leti, including a ReRAM-based spiking neural-network demonstration in 2019. Matrix extends that research direction by making a defined hardware platform available to additional qualified researchers.

Neuromorphic researcher Kevin D. Johnson, whose work includes heterogeneous and neuromorphic computing, said he wants to use the platform to validate models against actual hardware and assess system-level accuracy, latency, and power consumption. His interests include combining ReRAM with other processing technologies.

That approach reflects the practical opportunity: identify which parts of a workload benefit from memory-based computation, then combine them with other hardware where appropriate. The research question is broader than whether an individual operation is efficient; it includes whether the resulting system delivers useful and repeatable application performance.

Weebit also highlights radiation tolerance as a reason to investigate ReRAM for harsh environments. Suitability for a particular aerospace, defense, or medical deployment would still depend on the requirements and validation of the complete design.

Demonstrations and Research Access

Weebit plans to demonstrate Matrix IMC at electronica 2026, taking place November 10–13 in Munich. The company lists Hall C2, stand 637, with demonstration and meeting details on its event page.

The packages are available to qualified researchers, and applications will be evaluated for alignment with the program’s research focus. Weebit provides a research-project application form for prospective participants.

Matrix’s immediate contribution is access to hardware that can test the assumptions behind in-memory AI. For a field built around reducing the cost of moving data, the valuable evidence will be how measured accuracy, energy use, and latency hold up together when researchers run real workloads.

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