1. 引言：当脑仿真撞上算力墙
计算神经科学一直有个尴尬的现实：我们对大脑的理解越深入，构建的模型就越庞大，而跑动这些模型所需的算力增长得比模型本身还快。一个包含数百万神经元、数十亿突触的皮层网络模型，在传统 GPU 集群上仿真一秒钟的生物时间，往往需要几分钟甚至几小时的真实时间。
这意味着什么？意味着研究者想验证一个假设，可能要等上几天；意味着闭环脑机接口、实时神经调控这类对时延敏感的应用，几乎无法在纯软件仿真框架下落地。
本文要讨论的，是一条正在被验证的破局路径：用相变忆阻器（PCM）构建存内计算阵列，把脑动力学仿真的单步时延压到 2.12 毫秒，相比 GPU 实现 50–478 倍的加速。我们会从 GPU 的瓶颈讲起，拆解忆阻器"可控存内计算"的范式，再落到技术指标与应用验证，最后谈谈从实验室走向产业化的现实路径。
2. 传统 GPU 在脑动力学仿真中的算力瓶颈
2.1 冯·诺依曼架构的"存储墙"
GPU 擅长的是规则、稠密、可并行的浮点运算，而脑动力学仿真的核心负载恰恰不太"规则"：
- 稀疏连接：皮层网络的连接矩阵极度稀疏，GPU 的稠密矩阵乘法单元利用率被严重浪费；
- 事件驱动：脉冲神经网络（SNN）中神经元只在膜电位越过阈值时才发放脉冲，计算是稀疏且异步的；
- 状态耦合：每个神经元都要维护膜电位、恢复变量、突触电流等多组状态，状态读写量与计算量同量级。
在冯·诺依曼架构下，计算单元与存储单元分离，每一次状态更新都要把数据在片外 DRAM 与计算核心之间搬运一遍。访存带宽而非浮点算力，成了真正的天花板。
下图对比了冯·诺依曼架构下脑仿真单步更新的数据流，可以看到权重与状态在存储与计算之间反复搬运：
flowchart LR
A["片外 DRAM<br/>（权重 + 神经元状态）"] -->|"读取权重与状态"| B["计算核心<br/>（突触电流 / 膜电位更新）"]
B -->|"写回新状态"| A
B --> C["脉冲事件队列"]
C -->|"下一时间步"| B
2.2 时间步进带来的串行开销
脑动力学仿真通常采用数值积分（如 Euler、RK4）做时间步进。每一步都要完成：
- 读取全部神经元与突触状态；
- 计算突触电流与膜电位更新；
- 写回新状态；
- 处理脉冲事件与路由。
步与步之间存在严格的数据依赖，无法跨步并行。即便单步内部可以并行，单步的访存延迟与同步开销也会被放大到整个仿真时长上。这就是为什么很多 GPU 加速的仿真器在神经元规模上去之后，加速比迅速饱和。
时间步进的串行依赖关系可以更直观地表示为：
flowchart TD
T0["第 t 步：读取状态"] --> T1["计算突触电流"]
T1 --> T2["更新膜电位"]
T2 --> T3["写回状态"]
T3 --> T4["脉冲事件路由"]
T4 -->|"严格数据依赖，不可跨步并行"| T5["第 t+1 步：读取状态"]
2.3 能效比的天花板
除了速度，功耗同样是硬约束。人脑功耗约 20 W，而同等神经元规模的 GPU 集群动辄数十千瓦。对于需要长时间在线运行的类脑应用（如植入式神经调控、边缘端智能感知），GPU 方案的能效比根本无法接受。
3. 相变忆阻器的"可控存内计算"新范式
3.1 为什么是相变忆阻器
忆阻器家族里，相变存储器（Phase Change Memory, PCM）有几个特别适合脑仿真的属性：
- 多值电导：通过控制晶态/非晶态比例，器件电导可以连续调节，天然对应突触权重；
- 非易失：断电后权重保持，无需反复刷新；
- 可累积：器件对脉冲的响应具有累积效应，与生物突触的积分特性高度相似；
- 工艺成熟：PCM 已在存储产业中量产验证，具备工程化基础。
3.2 存内计算：把"搬运"变成"就地累加"
忆阻器交叉阵列（crossbar array）的物理结构本身就是一次矩阵向量乘法：输入电压施加在字线上，输出电流在比特线上按基尔霍夫电流定律自然求和。
V1 V2 V3
| | |
┌────┴───┬───┴───┬───┴───┐
WL1 ─┤ G11 │ G12 │ G13 ├─→ I1 = V1·G11 + V2·G12 + V3·G13
├────────┼───────┼───────┤
WL2 ─┤ G21 │ G22 │ G23 ├─→ I2 = V1·G21 + V2·G22 + V3·G23
└────────┴───────┴───────┘
这意味着突触权重的读取与乘加运算在同一个物理位置完成，彻底消除了权重搬运的访存开销。
3.3 "可控"二字的关键
纯粹的模拟存内计算有个老问题：器件非理想性（电导漂移、写噪声、非线性）会让长时间仿真累积误差。所谓"可控存内计算"，核心在于：
- 闭环校准：定期读取器件电导并与目标权重比对，通过写验证（write-verify）修正漂移；
- 混合精度策略：对精度敏感的膜电位积分放在数字域，对精度宽容的突触加权放在模拟域；
- 事件驱动调度：只在有脉冲事件时激活对应行列，进一步降低动态功耗。
这种"模拟做加权、数字做积分、闭环做校准"的分工，是让忆阻器仿真既快又准的关键设计。
这套分工可以用一张图概括：
flowchart LR
subgraph SIM["模拟域（忆阻器阵列）"]
M1["突触加权求和<br/>高并行、低精度"]
end
subgraph DIG["数字域（片上数字单元）"]
D1["膜电位积分<br/>高精度"]
D2["脉冲事件调度"]
end
subgraph CAL["闭环校准"]
C1["读取电导"] --> C2["与目标权重比对"]
C2 --> C3["write-verify 修正漂移"]
end
M1 --> D1
D1 --> D2
D2 -->|"脉冲反馈"| M1
C3 -->|"修正权重"| M1
4. 单步时延 2.12 毫秒的技术突破与 50–478 倍加速
4.1 指标拆解
加速比之所以是一个区间而非定值，是因为它强烈依赖网络规模与连接稀疏度：网络越大、越稀疏，GPU 的访存浪费越严重，忆阻器方案的优势就越明显。
4.2 时延构成分析
2.12 ms 的单步时延大致可以拆成几块：
- 模拟阵列计算：交叉阵列完成突触电流求和，耗时由阵列规模与 ADC 转换速度决定；
- 数字积分：膜电位与恢复变量的数值更新，在片上数字单元完成；
- 脉冲路由：事件分发与地址映射，采用片上网络（NoC）实现；
- 校准开销：周期性 write-verify 带来的额外时间，通过异步执行隐藏。
值得注意的是，ADC/DAC 转换往往是模拟存内计算的主要时延与功耗来源，这也是后续优化的重点方向。
按各环节的耗时占比，单步时延的构成大致如下：
pie showData
title "2.12 ms 单步时延构成（示意）"
"模拟阵列计算与 ADC 转换" : 45
"数字积分" : 25
"脉冲路由" : 20
"校准开销（异步隐藏后）" : 10
4.3 与 GPU 方案的对比逻辑
flowchart LR
subgraph GPU["GPU 方案"]
A1["读取权重<br/>（片外 DRAM）"] --> A2["稠密矩阵乘"]
A2 --> A3["写回状态"]
A3 --> A4["脉冲处理"]
A4 --> A1
end
subgraph PCM["忆阻器方案"]
B1["电压施加<br/>（权重就地）"] --> B2["电流求和<br/>（模拟域）"]
B2 --> B3["数字积分"]
B3 --> B4["事件路由"]
B4 --> B1
end
GPU 路径中，权重读取与状态写回占据了大部分时间；忆阻器路径把权重访问"物理消除"，剩下的主要是模拟转换与数字积分，这就是数量级差异的来源。
5. 脑皮层重建等应用场景的验证结果
5.1 皮层微电路重建
在皮层柱（cortical column）级别的重建任务中，研究者用忆阻器阵列承载重建出的突触连接矩阵，验证了：
- 网络自发活动模式（如 UP/DOWN 状态转换）与生物实验数据在统计特征上吻合；
- 长时间仿真（数分钟生物时间）下，权重漂移被闭环校准有效抑制，活动统计未出现明显发散。
5.2 脉冲神经网络推理
在 SNN 推理任务上，忆阻器方案在保持精度损失可控（通常 <1–2%）的前提下，把推理时延与能耗同时压下来，适合边缘端的实时感知场景。
5.3 闭环神经调控
这是对时延最敏感的场景。毫秒级的单步时延意味着仿真系统可以跟上真实神经信号的节律，实现"感知—仿真—刺激"的闭环。传统 GPU 方案在这个环节往往因为时延过大而只能做离线分析。
5.4 验证中的共性结论
综合来看，验证结果指向同一个结论：忆阻器方案的优势随规模与稀疏度增长而放大，在小规模稠密网络上优势有限，但在大规模稀疏皮层网络上优势显著。这也决定了它的落地场景选择。
不同场景对忆阻器方案的适配度可以这样归纳：
flowchart LR
R["忆阻器脑仿真方案"] --> S1["皮层微电路重建<br/>统计特征吻合"]
R --> S2["SNN 推理<br/>精度损失 毫秒级实时闭环"]
S1 --> K["优势随规模与稀疏度放大"]
S2 --> K
S3 --> K
6. 类脑计算从实验室到产业化的路径
6.1 当前的主要障碍
- 器件一致性：阵列内器件间的电导分布差异，直接影响仿真精度；
- 外围电路开销：ADC/DAC、校准电路、路由网络占据了相当面积与功耗；
- 工具链缺失：缺少成熟的编译器与仿真框架，算法到硬件的映射仍高度依赖人工；
- 良率与可靠性：大规模阵列的良率与长期漂移特性仍需产业验证。
6.2 分阶段落地路线
flowchart TD
S1["阶段一：专用加速卡<br/>面向科研仿真"] --> S2["阶段二：混合架构<br/>模拟加权 + 数字控制"]
S2 --> S3["阶段三：边缘端类脑芯片<br/>低功耗实时感知"]
S3 --> S4["阶段四：大规模神经形态系统<br/>闭环脑机接口"]
- 阶段一：以 PCIe 加速卡形态切入科研市场，替代部分 GPU 仿真任务，用真实负载打磨工具链；
- 阶段二：采用模拟/数字混合架构，把精度敏感部分留在数字域，降低对器件一致性的要求；
- 阶段三：面向边缘端低功耗场景，发挥非易失与事件驱动的能效优势；
- 阶段四：在器件与工具链成熟后，进入闭环脑机接口等对时延与功耗双敏感的高价值场景。
6.3 生态建设的关键
产业化不只是硬件问题。真正决定成败的是软件栈：能否让神经科学家用熟悉的模型描述语言（如 PyNN、NEST 的模型定义）直接映射到忆阻器阵列，能否提供自动化的精度—能效权衡工具。硬件性能再亮眼，如果迁移成本过高，也很难被科研社区采纳。
7. 总结
回到开头的问题：脑动力学仿真的算力瓶颈，本质上是冯·诺依曼架构下"权重搬运"的瓶颈。相变忆阻器通过存内计算把这一步物理消除，配合闭环校准与混合精度策略，把单步时延压到 2.12 毫秒，换来 50–478 倍的加速。
这条路还远未走完——器件一致性、外围开销、工具链缺失都是实打实的障碍。但方向是清晰的：当计算发生在数据所在的地方，脑仿真的时间尺度才有可能真正逼近生物本身的时间尺度。
对于关注类脑计算的开发者，建议从两个方向切入：一是跟踪忆阻器阵列的精度校准方法，二是关注神经形态编译工具链的进展——这两者决定了这项技术何时能从论文走进产品。
本文由 AI图鉴自动抓取并翻译，版权归原作者所有；如需查看原文请点下方链接。
1. Introduction: When a brain is mimicing into a calculus Wall
There's always an awkward reality in computational neuroscience: the deeper we understand the brain, the bigger the models we build, and the faster the calculus we need to run these models than the models themselves. A cortical network model with millions of neurons, billions of synapses, imitating one second of biological time in traditional GPU clusters, often takes minutes, if not hours.
What does that mean? This means that researchers want to validate a hypothesis that may take days to wait; it means that closed loop brain interfaces, real-time neuroregulations, such as sensitive applications such as latency, are virtually impossible to locate in a purely software simulation framework.
What we are discussing here is a proven break-through path: building a memory array with a phase amnesifier (PCM) that really presses brain dynamics simulations to a single step of Z102Z to 2.12 milliseconds, which is 50-478 times faster than GPU. We'll start with the GPU bottlenecks, remove the memory retardator's "controllable in-house computing" paradigm, turn to technical indicators and application validation, and end with a realistic path from laboratory to industry.
2. Traditional GPU calculator bottlenecks in brain power simulations
2.1 von Neumann's "store wall"
GPU is good at rules, dense, parallel floating-point calculations, and the core load of brain dynamics simulations is not exactly "rules":
- Rare connectivity: the connectivity matrix of the cortical network is extremely thin and the utilization of the dense matrix multiplication unit of the GPU is severely wasted;
- Event driven: neurons in the pulse nervous network (SNN) only distribute pulses when the membrane level has crossed the threshold, calculated as thin and variable;
- State coupling: each neuron is required to maintain a multi-group state such as membrane level, recovery variable, synapse current, and state reading and writing is equal to calculation.
Under the von Neumann structure, the computing unit is separated from the storage unit, and each state update moves the data between the outer DRAM and the computing core. The access bandwidth, rather than floating point computing, became the real ceiling.
The figure below compares the one-step data stream of the von Neumann structure, where the weight and state are being moved repeatedly between storage and computation:
flowchart LR
A["Extra DRAM<br/> (weight + neuron state)" -- >"Read weight and state" | B["calculating core <br/> (intuitive current / membrane level update)"]
"B--"B--"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"-"--"-"-"--"-"-"-"-"---------------
B-C.
"C--"Next step." "B."
2.2 Serial costs of time progression
Brain dynamics simulations usually use numerical points (e.g. Euler, RK4) for time progression. Each step must be completed:
- Read all neurons and synapses;
- Calculation of synaptic currents and membrane level upgrading;
- Write back the new status;
- Deal with pulse events and route.
There is a strong data dependency between steps, which does not allow for parallel steps. Even if a one-step in-house can be paralleled, a one-step delay in access and synchronized costs can be magnified over the entire simulation period. That's why many GPU acceleration imitators are faster than saturated after neurons are on scale.
The symbiotic dependency of time steps can be more intuitive:
flowchart TD
T-0 ["T-step: read state"]--"T1"
T1-- > T2
T2... > T3
T3- > T4.
T4-------------------------------------------------------------------------------------------------------------------------- and-----------------------------------------------------------------------------------------------------------------------------------
2.3 The energy efficiency ratio ceiling
In addition to speed, it is also hard to limit. The human brain is about 20 W, and the GPU clusters of the same neurons are tens of kilowatts. The GPU energy efficiency ratio is not acceptable for brain type applications that require long online operation (e.g. implanted neuroregulation, marginal intelligence perception).
3. New paradigm for "controlled memory computing" for phase amnesifiers
3.1 Why amnesia? Device
There are several properties in the family of amnesia that are particularly suitable for brain imitation:
- Multi-value conductor: through control of the crystal/non-crystal ratio, the device is continuously calibrated and naturally corresponds to the synaptic weight;
- Not vulnerable: weights after power outages are maintained without repeated updating;
- Accumulation: the response of the device to pulses has a cumulative effect and is similar to the biological synapses;
- Process maturity: PPM has been certified in the storage industry for mass production and has a engineering basis.
3.2 Storage calculations: replace "handling" with "local accumulation"
The physical structure of the cross-crossbar array is itself a matrix vector multiplication: the input voltage is applied to the font line, and the output current is reconciled on the Bitline by the law of the Kirhoff current.
V1 V2 V3
| | |
┌────┴───┬───┴───┬───┴───┐
WL1 ─┤ G11 │ G12 │ G13 ├─→ I1 = V1·G11 + V2·G12 + V3·G13
├────────┼───────┼───────┤
WL2 ─┤ G21 │ G22 │ G23 ├─→ I2 = V1·G21 + V2·G22 + V3·G23
└────────┴───────┴───────┘
This means that the read-and- times-calculation of the tactile weight is done in the same physical position, completely eliminating the cost of access to the load.
3.3 Key to the word "controllable"
There's an old problem with pure simulation memory calculations: the non-ideality of the device (conductive drift, noise writing, non-linear) allows for cumulative errors of simulation over time. The core of the so-called controlled memory calculations is:
- Closed ring calibration: periodic reading of the device electrically and against target weights, correction of drift through writing validation (write-verify);
- Mixed precision policy: the membrane-sensitive electron fraction is placed in the digital domain and the synaptic weight of precision tolerance is placed in the analog field;
- Incident-driven movement: only the corresponding array is activated when there is a pulsed event, further reducing the dynamic effort.
This division of "simulation for weighting, digital scoring, closed loop calibration" is the key design for reminiscing memory.
This division of labour can be summarized in a graph:
flowchart LR
Subgraph SIM
M1 ["Smoke weighting and <br/> High Parallel, Low Precision"]
end
Subgraph DIG ["digital domain (number unit on film)"]
D1 ["Membrane EMP <br/> High precision"]
D2.
end
Subgraph Cal.
C1 ["Reading Guides"]-- > C2["and target weights"]
C2 -- > C3 ["write-verify drifting]
end
M1 --> D1
D1 --> D2
D2------------------------------------------------------------------------ and-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
"C3--"Revision weight" "M1"
4. One-step latency 2.12 millisecond technological breakthrough and 50-478 times acceleration
4.1 Dismantling of indicators
The acceleration ratio is an interval rather than a fixed value, because it relies heavily on network size and connection thinness: the larger the network, the less it is, the more the GPU's access is wasted, the more obvious the benefits of the memory device programme.
4.2 latency Composition Analysis
2.12 ms single-step latency can be roughly split into pieces:
- Simulation of array calculations: cross-array completion of synaptic current demand, time-consuming determined by array size and ADC conversion speed;
- Digital fraction: numerical updating of the membrane level and restoration variable, completed in the digital unit on the film;
- Pulse routing: event distribution and address mapping, achieved through a piece of web (NoC);
- Calibration expenses: additional time brought by cyclical write-verify, hidden by walk.
It is noteworthy that ADC/DAC conversions are often the main source of latency and power consumption for modelling memory calculations, which is also the main orientation for subsequent optimization.
The composition of single-step latency is as follows:
pie showData
Title "2.12 ms One Step latency Composition"
Simulation array calculation and ADC conversion: 45
Digital score: 25
Pulse route: 20.
Calibration expenses (sliding behind): 10
4.3 Comparative logic with the GPU programme
flowchart LR
Subgraph GPU.
A1 ["Read weight <br/> (outside DRAM")] ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A2-- > A3.
A3- > A4.
A4 --> A1
end
Subgraph PCM
B1 ["Pression of voltage <br/> (weight in situ)"] -- > B2 ["electric current demand and <br/> (simulation domain)"]
B2- > B3 ["digital points"]
B3-- > B4.
B4 --> B1
end
In the GPU path, weight reading and status writing take most of the time; the memory-retarder path accesss the "physical elimination" of weight, and the rest is mainly analogue conversions and numerical points, which are the source of the quantitative difference.
5. Validation of applications such as the reconstruction of the cortex
5.1 Re-establishment of cortical microcircuits
In a reconstruction mission at the level of cortical column, researchers validated the re-established synaptic connectivity matrix with amnesia arrays:
- Compatibility of the mode of spontaneous network activity (e.g., UP/DOWN status conversion) with the statistical characteristics of biological experimental data;
- Under long-term simulations (minutes of biological time), weight drift is effectively inhibited by closed ring calibration and activity statistics are not significantly dispersed.
5.2 Pulse nervous network reasoning
In the SNN reasoning task, the amnesia program, while maintaining the accuracy of the loss controllable (usually < 1-2 per cent), crushes the reasoning latency at the same time as energy consumption and is suitable for a marginal real-time perception scenario.
5.3 Closed circle neuroregulation
This is the most sensitive scene to latency. One-step latency in milliseconds means that a simulation system can keep up with the rhythm of a real neural signal and achieve a "sensitization-impression-stimulation" loop. The traditional GPU program is often too large to do offline analysis at this point.
5.4 Common findings in validation
Taken together, the validation results point to the same conclusion: the advantages of the amplifier programme are amplified by increasing size and thinness, with limited advantages in small dense networks, but with significant advantages in large-scale swirling cortex networks. It also determines its landing site selection.
The adaptation of different scenarios to amnesia programs can be summarized as follows:
flowchart LR
R ["Remembracing Brain Simulator"]--------------------------------------------------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
R->S2 ["SNN reasoning loss of accuracy <br/> ms real-time closure"]
S1 -- > K["Empowers amplified with Size and Slattery"]
S2 --> K
S3 --> K
6. Paths from laboratory to industrialization of brain type computing
6.1 Current main obstacles
- Consistency of devices: differences in the electrical distribution of devices within arrays, which directly affect the imitation accuracy;
- External circuit expenses: ADC/DAC, calibration of circuits, route network occupied considerable area and utility;
- Lack of tool chains: lack of a mature compiler and simulation framework, and high reliance on manual mapping of algorithms to hardware;
- Probability and reliability: The probabilities and long-term drift characteristics of large arrays still need to be validated by industry.
6.2 Phased landing routes
flowchart TD
S1 ["Step I: dedicated accelerator <br/> for scientific simulation" -- >S2 ["Step II: Mixed Structure <br/> Simulation weight + Digital Control"]
S2 -- > S3 ["Step III: Peripheral brain chips <br/ > Low-power real-time perception"]
S3->S4 ["Phase IV: Large-scale neuromorphological system <br/> closed ring brain interface"]
- Phase one: cutting into the scientific research market in the form of PCIe accelerator cards, replacing part of the GPU simulation mission and grinding the tool chain with a real load;
- Phase II: the introduction of analogue/digital hybrid structures to keep the precision sensitive parts in the digital domain and to reduce the requirement for consistency of devices;
- Phase III: Energy efficiency advantage driven by non-removable and event-driven scenarios for marginal low-capacity scenarios;
- Phase 4: High-value scenarios sensitive to both latency and utility, such as closed ring brain interfaces, once the equipment and tool chains mature.
6.3 Keys to ecological construction
Industrialization is not just a matter of hardware. What really determines success is the software warehouse: whether neuroscientists can use familiar models to describe languages (e.g. PyNN, NEST definition) to map directly into memory arrays, and whether they can provide automated precision-energy efficiency trade-offs. Hardware performance is becoming more visible and, if migration costs are too high, it is difficult for scientific communities to adopt it.
7. Summary
Turning back to the question at the beginning: the simulation of brain dynamics really counts as a bottleneck, which is essentially a bottleneck of "weighting" under von Neumann. The amnesifier removes this step physically by means of memory calculations, matching the closed ring calibration and mixing precision policy, pressing one-step latency to 2.12 milliseconds in exchange for 50-478 times acceleration.
The road is far from complete — the consistency of the device, the cost of the outer space, and the absence of the tool chain are real obstacles. But the direction is clear: when the calculation takes place where the data are located, it is possible to imitate a real time scale for the brain to actually approach the time scale of the organism itself.
For developers concerned with brain computing, it is suggested to move in two directions: tracking precision calibration methods for amnesia arrays, and focusing on the progress of the neurological compilation tool chain, which determines when the technology can enter the product from the paper.
Auto-fetched and translated by AI Atlas. All rights belong to the original author.