OCT. 20, 2026 (英语).
一些对AI最有说服力的使用案例正直接发生在我们周围的装置上。 在个人设备中首先看到它，比如需要实时理解上下文的可穿戴设备，在企业和工业系统中，如自主机器人和智能传感器中，它也越来越多。 这些经历需要低纬度，严格的隐私，以及全天的可靠性，这些可靠性不能依赖不断的往返到云端。
Edge AI补充云，带来最好的AI体验。 这些系统依靠连续不断的上下文和情报流动，在正确的时间在正确的地点收集和处理信息。 边缘的超低功率模型可以持续感应和实时响应，同时当需要更深的推理时，可以无缝地传递给更大的端侧或云模型。
然而，建造边墙比应该的要困难得多。 虽然云基础设施已经围绕几个标准软件堆叠而汇合，但边缘被分割成数百个专有芯片架构和不兼容的工具链。 对于 ML 开发者来说，这创造了沉重的破碎税，在那里你最终会重写内核，重新量化模型，并调试每个目标芯片的供应商专用编译器。
去年，Google Research 推出 Coral NPU有了简单的想法：开放的硬件和软件标准是统一边缘，解锁开发者生产力和可移植性的唯一途径。 我们基于标准，ML-First RISC-V架构与可靠的开源工具链对齐，让开发者相信他们的模型会编译和运行，让团队一次优化一个模型，并在不同的SoC供应商，设备和电源封套上部署。
今天，我们正在珊瑚努力中达到三个主要里程碑：
- 完整的32位珊瑚NPU架构(Milestones 1–4)：包括我们新的母体执行组最多可配置1超过并瞄准10mW的平均能量进行推断
- 珊瑚编译器 v1.0，基于IREE/MLIR：开源，端对端编译器和模拟堆栈将JAX,PyTorch,TensorFlow模型直接带到珊瑚NPU硬件目标。
- 新的MCU芯片，配有Coral NPU：解析2-gen Synaptics Astra® SR200系列(400 GOPS)微控制器芯片。
- 新的珊瑚板工具包：新的珊瑚板TM SR的发布，加上来自DigiKey的珊瑚板SL(1超过)的全球可用性。
修复边缘的破碎比发布指令集要多。 历史上，许多边缘加速器被设计成在光谱板上击打高峰计算数字，让编译组日后去计算软件支持。 在实际操作中，不支持的神经网络层会回落到通用CPU，这可以伤害耐久性和排水电池。
我们从一开始就一起设计了珊瑚NPU架构及其编译器。 而不是追求峰值度量衡，我们的焦点是能动计算：帮助在合适的电源信封上为您的应用提供正确的性能。
在过去的一年中，我们发布是32位珊瑚NPU设计的前三个里程碑：用于控制流的可编程的RISC-V Scalar前端(Milestone 1)，用于SIMD操作的RV v1.0矢量协同处理器(Milestone 2)，以及具有浮点支持的紧密结合的内存子系统(Milestone 3). 随着本月发布矩阵执行单元(Milestone 4),32位架构完成。
Scalar和矢量单元对于一般的控制逻辑和信号处理是巨大的，但现代的ML工作量——从视觉编码器到变压器的注意层——将其大部分时间花在2D矩阵-矩阵(GEMM)和矩阵-变量(GEMV)乘法上。 在1D向量引擎上运行2D矩阵数学迫使芯片从内存中反复加载重量和激活，这可能意味着花费更多的能量移动数据而不是做数学。
我们的矩阵执行股利用RISC-V VME规格(形式上是Zvt家族的一部分)来满足这一需要，并使用专用的外产倍积(MAC)引擎。 由于外产发动机在单个周期(每周期256MAC)中计算出一整块2D瓦的操作，它直接在本地登记册中重新使用权重和激活。 这种带来四进制的吞吐量放大到核心，可配置最多1超过。
在子-10 mW信封中拥有一个专用矩阵引擎会改变开发者可以在一个小电池上建立什么。 设备与其停留在简单的关键词标注或基本运动探测上，不如运行连续的，多模式的工作量，包括Gemma，实时等紧凑变压器模型在可穿戴器上的语音翻译，可听器上的空间音频过滤，机器人上的低纬度视觉感知。
为了帮助硅组将这种开放式设计直接投入商业生产，完整的32位RTL今天可以在GitHub上提供。
为了方便硬件在不写入自定义组装的情况下瞄准，我们还在释放我们的开源 MLIR/IRE编译器工具链的v1.0基础。
有了这个堆栈，就可以通过StableHLO和TOSA等标准表示，从JAX,PyTorch，或TensorFlow带来模型。 编译器在主机CPU和Coral NPU核心之间的工作量分配，处理操作员聚变，瓦片矩阵以适应本地的SRAM和矩阵累积器，并逐渐将工作量直接降低到Coral NPU scalar,RVV v1.0向量，以及VME矩阵指令。 除了我们的开源 MPACT模拟器和参考FPGA设计外，硬件和软件团队可以在芯片开始制造之前，使用基准测试模型和调音硅配置。
将开放标准转化为商业硅将对整个半导体价值链进行协作。 为了帮助硅伙伴将这种开放设计直接带入商业生产，今天在GitHub上可以获得完整的32位的RTL，我们正与VeriSilicon合作进行设计实施和验证(DV)，以确保硅磁带的通关准备。 我们还在与全球基金会合作，研究其12LP+ FinFET进程 - 加速核心时间的70%，并在整个RTL迭代中将标准细胞面积减少高达15%，同时正在为矩阵执行单位评价12LP+超低功率库。
在商业硅方面，我们与Synaptics 显示的合作如何迅速将这个开放的标准转换成真正的硬件跨越非常不同的动力预算而不分割软件的经验。
在Synaptics Tech Day(2026年10月20日),Synaptics是发布三款基于Coral NPU技术，并由开放的IRE/MLIR工具链支持的商业硅和硬件产品：
- 2th-Gen硅—突触Astra SR200系列：本月磁带和发布，SR200系列集成第二代珊瑚NPU IP(包括里程碑2 RISC-V矢量核心支持)，在超低功率MCU包中交付400 GOPS. 它是为电池动力的可穿戴设备和工业传感器节点而建造的。
- 新的突触珊瑚板SR 发布：由Astra SR200系列提供动力的新珊瑚板SR开发者工具包，旨在快速原型化MCU级边缘和物理AI应用。
- Synaptics Coralboard SL Reaches General Problicity(GA)：继我们在Google I/O的有限版预览后，Coralboard SL现在一般通过DigiKey在全球范围提供，SDK和文档在Synaptics Coralboard开发者页面上。 由Astra SL2619处理器提供动力，并配有1个超过 TorqTM / Coral NPU子系统，其带来变压器和多流视加速器配属至Linux基于IOT和机器人。
因为两个产品家族都建立在相同的架构和编译器基础上，ML团队可以一次优化一个模型，并部署到一个毫瓦级的可穿戴(Coralboard SR)或使用同一工作流程的1超过板(Coralboard SL). 与硬件和System-on-Module partner Grinn合作开发的Coralboard排队也为团队提供了从devkit原型到商业生产硬件的直接路径。
随着我们的32位架构和v1.0编译器堆栈的到位，我们已经在进行下一阶段的路线图，包括64位Coral NPU架构和CHERI对安全的支持。
无论是在设计自定义边缘 SoC，在 ML 编译器上工作，还是在可穿戴和机器人上部署模型，Coral NPU 都可以帮助给您一个从模型到硅的开放路径。 在这里你可以开始：
- 阅读文件：访问开发者.google.com/做建筑指南、文档和教程。
- 探索代码：检查完整的32位RTL(包括里程碑4矩阵执行单元),v1.0 IREE/MLIR编译器堆栈，以及GitHub上的MPACT模拟器。
- 获得devkit：在DigiKey上订购今天普遍可用的突触珊瑚板SL，并在突触珊瑚板开发者页面上探索新的Astra SR200系列和珊瑚板SR.
我们要感谢对这项工作的核心贡献者和领导团队，特别是：比利·拉特利奇、本·劳里、德里克·周、摇摆弗卢尔、亚历克斯·范达姆、比拉尔汗、大卫·加奥、格雷戈里·基连、朱利安·穆林斯-布莱克、卡莱德·塔拉克德、伦东、马修·威尔逊、迈克尔·霍恩、穆拉里·维贾亚拉哈万、纳维·多达、罗曼·卢考、斯特凡·霍尔、托尔·耶雷米森、王延凯、玛尼亚·达萨里、阿基布·乌丁、迪维亚·潘迪亚、史蒂夫·贺、普德雅、普雷蒂·辛格、安东尼·法伦、汉斯·雷佩尔、埃斯梅拉尔达·卡德纳斯、伊沙·米什拉、凯·齐马、雷廷·帕里赫、汉纳·拜尔·鲁兴、泰勒·蒙哥马利、凯伊克、斯穆罗尔、辛迪、刘邦、邦菲·潘、阿莱克、格、杰夫·斯特林、罗宾·杜亚、高
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OCT. 20, 2026
Some of the most compelling use cases for AI are happening directly on the devices around us. You see it first in personal devices like wearables that need to understand context in real time, and increasingly in enterprise and industrial systems like autonomous robots and smart sensors. These experiences require low latency, strict privacy, and all-day reliability that cannot depend on a constant round-trip to the cloud.
Edge AI complements the cloud to bring the best AI experiences. These rely on a continuous flow of context and intelligence across both, working as a model cascade where information is captured and processed in the right place at the right time. Ultra-low-power models on the edge can continuously sense and respond in real time, while seamlessly handing off to larger on-device or cloud models when deeper reasoning is needed.
Still, building for the edge is much harder than it should be. While cloud infrastructure has converged around a few standard software stacks, the edge is split across hundreds of proprietary chip architectures and incompatible toolchains. For ML developers, this creates a heavy fragmentation tax, where you end up rewriting kernels, re-quantizing models, and debugging vendor-specific compilers for every chip you target.
Last year, Google Research introduced Coral NPU with a simple idea: an open hardware and software standard is the only way to unify the edge and unlock developer productivity and portability. Our standards based, ML-first RISC-V architecture paired with a reliable open-source toolchain gives developers confidence that their models will compile and run, letting teams optimize a model once and deploy it across different SoC vendors, devices, and power envelopes.
Today, we are reaching three major milestones in the Coral effort:
- The complete 32-bit Coral NPU architecture (Milestones 1–4): Including our new Matrix Execution Unit, configurable for up to 1 TOPS and targeting 10mW average power for inference.
- The Coral Compiler v1.0, based on IREE/MLIR: An open-source, end-to-end compiler and simulation stack that takes JAX, PyTorch, and TensorFlow models straight to the Coral NPU hardware target.
- New MCU chip with Coral NPU: Unveiling the 2nd-gen Synaptics Astra® SR200 series (400 GOPS) microcontroller chips.
- New Coralboard kits: Launching the new Coralboard™ SR, plus global availability of the Coralboard SL (1 TOPS) from DigiKey.
Fixing fragmentation at the edge takes more than publishing an instruction set. Historically, many edge accelerators were designed to hit high peak-compute numbers on spec sheets, leaving compiler teams to figure out software support later. In practice, unsupported neural network layers fall back to a general-purpose CPU, which can hurt latency and drain the battery.
We designed the Coral NPU architecture and its compiler together from the start. Instead of chasing peak metrics, our focus is on energy-viable compute: helping to deliver the right performance at the right power envelope for your application.
Over the past year, we released the first three milestones of the 32-bit Coral NPU design: a C-programmable RISC-V scalar frontend for control flow (Milestone 1), an RVV v1.0 vector co-processor for SIMD operations (Milestone 2), and a tightly coupled memory subsystem with floating point support (Milestone 3). With this month's release of the Matrix Execution Unit (Milestone 4), the 32-bit architecture is complete.
Scalar and vector units are great for general control logic and signal processing, but modern ML workloads—from vision encoders to transformer attention layers—spend most of their time on 2D matrix-matrix (GEMM) and matrix-vector (GEMV) multiplication. Running 2D matrix math on a 1D vector engine forces the chip to repeatedly load weights and activations from memory, which can mean spending more energy moving data than doing math.
Our Matrix Execution Unit leverages the RISC-V VME specification (formally part of the Zvt family) to address this need and uses a dedicated outer-product multiply-accumulate (MAC) engine. Because an outer-product engine computes a full 2D tile of operations in a single cycle (256 MACs per cycle), it reuses weights and activations directly inside local registers. This brings quadratic throughput scaling to the core, configurable for up to 1 TOPS.
Having a dedicated matrix engine in a sub-10 mW envelope changes what developers can build on a small battery. Rather than stopping at simple keyword spotting or basic motion detection, devices can run continuous, multimodal workloads, including compact transformer models like Gemma, real-time voice translation on wearables, spatial audio filtering on hearables, and low-latency visual perception on robots.
To help silicon teams bring this open design straight into commercial production, the complete 32-bit RTL is available today on GitHub.
To make the hardware easy to target without writing custom assembly, we are also releasing the v1.0 foundation of our open-source MLIR/IREE compiler toolchain.
With this stack, you can bring models from JAX, PyTorch, or TensorFlow through standard representations like StableHLO and TOSA. The compiler partitions workloads between the host CPU and the Coral NPU core, handles operator fusion, tiles matrices to fit local SRAM and matrix accumulators, and progressively lowers workloads directly to Coral NPU scalar, RVV v1.0 vector, and VME matrix instructions. Alongside our open-source MPACT simulator and reference FPGA design, hardware and software teams can benchmark models and tune silicon configurations before a chip ever goes to fabrication.
Turning an open standard into commercial silicon takes collaboration across the entire semiconductor value chain. To help silicon partners bring this open design straight into commercial production, the complete 32-bit RTL is available today on GitHub, and we are partnering with VeriSilicon on the design implementation and verification (DV) to ensure turnkey readiness for silicon tape-outs. We are also working with GlobalFoundries on their 12LP+ FinFET process - accelerating core timing by 70%, and reducing standard-cell area by up to 15% across RTL iterations, with ongoing evaluation of 12LP+ ultra low-power libraries for the Matrix Execution Unit.
On the commercial silicon side, our collaboration with Synaptics shows how quickly this open standard translates into real hardware across very different power budgets without splitting the software experience.
At Synaptics Tech Day (October 20, 2026), Synaptics is launching three commercial silicon and hardware products built on Coral NPU technology and supported by the open IREE/MLIR toolchain:
- 2nd-Gen Silicon — Synaptics Astra SR200 Series: Taped out and launching this month, the SR200 series integrates second-generation Coral NPU IP (including Milestone 2 RISC-V Vector Core support) to deliver 400 GOPS in an ultra-low-power MCU package. It is built for battery-powered wearables and industrial sensor nodes.
- New Synaptics Coralboard SR Unveiled: A new Coralboard SR developer kit powered by the Astra SR200 series, designed for rapid prototyping of MCU-class Edge and Physical AI applications.
- Synaptics Coralboard SL Reaches General Availability (GA): Following our limited-edition preview at Google I/O, the Coralboard SL is now generally available worldwide through DigiKey, with SDKs and documentation on the Synaptics Coralboard Developer page. Powered by the Astra SL2619 processor with a 1 TOPS Torq™ / Coral NPU subsystem, it brings transformer and multi-stream vision acceleration to Linux-based IoT and robotics.
Because both product families build on the same architecture and compiler foundation, ML teams can optimize a model once and deploy it to a milliwatt-class wearable (Coralboard SR) or a 1 TOPS board (Coralboard SL) using the same workflow. Developed in collaboration with hardware and System-on-Module partner Grinn, the Coralboard lineup also gives teams a direct path from devkit prototyping to commercial production hardware.
With our 32-bit architecture and v1.0 compiler stack in place, we are already working on the next phase of the roadmap, including a 64-bit Coral NPU architecture and CHERI support for security.
Whether you are designing a custom edge SoC, working on ML compilers, or deploying models to wearables and robotics, Coral NPU can help give you an open path from model to silicon. Here is where you can get started:
- Read the docs: Visit developers.google.com/coral for architecture guides, documentation, and tutorials.
- Explore the code: Check out the complete 32-bit RTL (including the Milestone 4 Matrix Execution Unit), the v1.0 IREE/MLIR compiler stack, and the MPACT simulator on GitHub.
- Get a devkit: Order the generally available Synaptics Coralboard SL today on DigiKey, and explore the new Astra SR200 series and Coralboard SR on the Synaptics Coralboard Developer page.
We would like to thank the core contributors and leadership team for this work, particularly Billy Rutledge, Ben Laurie, Derek Chow, Shaked Flur, Alex Van Damme, Bilal Khan, David Gao, Gregory Kielian, Julian Mullings-Black, Khaled Talukder, Lun Dong, Matthew Wilson, Michael Hoang, Murali Vijayaraghavan, Naveen Dodda, Roman Lewkow, Stefan Hall, Tor Jeremiassen, Yenkai Wang, Manya Dasari, Akib Uddin, Divya Pandya, Steve He, Preeti Singh, Anthony Phalen, Hans Rempel, Esmeralda Cardenas, Isha Mishra, Katy Zima, Resham Parikh, Hannah Bayer Rushing, Taylor Montgomery, Kai Yick, Srikanth Muroor, Cindy Liu, Bangfei Pan, Alec Go, Geoff Stirling, Robin Dua, Gaurav Arora, Steve Goldberg, Francesco Visin, Gus Martins, Ian Ballantyne, Kat Black, Ravin Kumar, Tris Warkentin, Avinatan Hassidim, Jay Yagnik, Katherine Chou, Shahram Izadi, and Yossi Matias.
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